1. Field of the Invention
This invention relates in general to the field of instruction execution in computers, and more particularly to an improved apparatus and method for executing a floating point exchange instruction within a microprocessor.
2. Description of the Related Art
A common instruction that is provided within a microprocessor is a floating point exchange instruction. The floating point exchange instruction allows a programmer to specify two operands to be swapped within a floating point register file. This is illustrated by the mnemonic FXCH R1,R2. More specifically, this instruction directs that the contents of a register R1 are to be written into a register R2, and that the contents of the register R2 are to be written into the register R1.
The floating point exchange instruction is widely used because many floating point instructions operate exclusively on an operand that must be present in a particular register in the floating point register file. The floating point exchange macro instruction provides a simple means of moving an operand to that particular register. Furthermore, it is not uncommon for a floating point exchange instruction that specifies an operand in the particular register to immediately follow a preceding floating point computational instruction that prescribes the particular register as a location for storage of its result. When this occurs, the operand specified by the floating point exchange instruction is dependent upon resolution of the preceding floating point computational instruction. That is, the operand specified by the floating point exchange instruction cannot be retrieved for the swap until the preceding floating point computational instruction writes its result back into the particular register.
When a dependency exists as stated above, control logic in the microprocessor typically delays the floating point exchange instruction in the floating point instruction pipeline, and does not allow it to access the particular register until the preceding floating point computational instruction writes its result back into that register. From the standpoint of program execution time, any delay in the instruction pipeline is undesirable. But this resolution delay is further compounded in a program that contains multiple dependent floating point exchanges. The time required to execute such a program is significantly impacted by the resolution delay incurred each time a dependent floating point exchange is executed.
Therefore, what is needed is an apparatus and method that allows a dependent floating point exchange to be executed faster than has heretofore been provided. Additionally, what is needed is an apparatus and method that allows a dependent floating point exchange to be executed without resolution delay. In addition, what is needed is a microprocessor that executes a floating point exchange without resolution delay which requires only minimal additional hardware.